//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
/*  Copyright 2002-2003 Intel Corp. */

#ifndef __BLRBITS_H
#define __BLRBITS_H


    /*  *********************************************
        This Header File defines the Bit Masks
        for Mainstone's Board Level Register (BLR)
        *********************************************
    */


    //
    //  Mainstone:  Board-Level Register Masks & Constants
    //

    //
    // DISC/BLANK LED (On=0, Off=1: read/write)
    //      {*Use 1's complement to turn ON}
    //
    #define DISC_LED0_MASK    	(1 << 0)
    #define DISC_LED1_MASK    	(1 << 1)
    #define DISC_LED2_MASK    	(1 << 2)
    #define DISC_LED3_MASK    	(1 << 3)
    #define DISC_LED4_MASK    	(1 << 4)
    #define DISC_LED5_MASK    	(1 << 5)
    #define DISC_LED6_MASK    	(1 << 6)
    #define DISC_LED7_MASK    	(1 << 7)

    //
    // GP SWITCHES (read-only) 1=noDOT, 0=DOT
    //
    #define SW12_MASK        (0x1 << 15)
    #define SW11_MASK        (0x1 << 14)
    #define SW7_MASK         (0x1 << 13)
    #define SW6_MASK         (0x1 << 12)
    #define SW10_MASK        (0x1 << 11)
    #define SW8_MASK         (0x1 << 10)
    #define SW4_MASK         (0x1 << 9)
    #define SW3_MASK         (0x1 << 8)
    #define HEXSW1_MASK      (0xF << 4)
    #define HEXSW0_MASK      (0xF)

    //
    // MISC_WR 1 (read/write)
    //

    // Masks
    //
    #define LCD_CTL_MASK    (0x1 << 13)
    #define MS_ON_MASK      (0x1 << 12)
    #define MMC_ON_MASK     (0x1 << 11)
    #define MS_SEL_MASK     (0x1 << 10)
    #define BB_SEL_MASK     (0x1 << 9)
    #define nBT_OFF_MASK    (0x1 << 8)
    #define BTDTR_MASK      (0x1 << 7)
    #define IRDA_MD_MASK    (0x3 << 5)
    #define IRDA_FIR_MASK   (0x1 << 4)
    #define GREEN_LED_MASK  (0x1 << 3)
    #define PDC_CTL_MASK    (0x1 << 2)
    #define MTR_ON_MASK     (0x1 << 1)
    #define SYSRESET_MASK   (0x1)

    // Constants
    //
    #define IRDA_MD_ONETHIRD    (0x3 << 5)
    #define IRDA_MD_TWOTHIRD    (0x2 << 5)
    #define IRDA_MD_SHUTDOWN    (0x1 << 5)


    //
    // MISC_WR 2 (read/write)
    //
    #define NUSBC_SC_MASK       (0x1 << 4)
    #define I2S_SPKROFF_MASK    (0x1 << 3)
    #define AC97_SPKROFF_MASK   (0x1 << 2)
    #define RADIO_PWR_MASK      (0x1 << 1)
    #define RADIO_WAKE_MASK     (0x1)


    //
    // MISC_RD (read-only)
    //
    #define nPENIRQ_MASK        (0x1 << 9)
    #define nMEMSTK_CD_MASK     (0x1 << 8)
    #define nMMC_CD_MASK        (0x1 << 7)
    #define nUSIM_CD_MASK       (0x1 << 6)
    #define USB_CBL_MASK        (0x1 << 5)
    #define TS_BUSY_MASK        (0x1 << 4)
    #define BTDSR_MASK          (0x1 << 3)
    #define BTRI_MASK           (0x1 << 2)
    #define BTDCD_MASK          (0x1 << 1)
    #define MMC_WP_MASK         (0x1)

    //
    // INTERRUPT MASK/ENABLE (read/write: 0=Mask, 1=Enable)
    //  AND
    // INTERRUPT SET/CLEAR (read/write: 0=Clear, 1=Set)
    //
    #define PCMCIA_S1_IRQ_MASK      (0x1 << 15)
    #define PCMCIA_S1_STSCHG_MASK   (0x1 << 14)
    #define PCMCIA_S1_CD_MASK       (0x1 << 13)
    #define PCMCIA_S0_IRQ_MASK      (0x1 << 11)
    #define PCMCIA_S0_STSCHG_MASK   (0x1 << 10)
    #define PCMCIA_S0_CD_MASK       (0x1 << 9)
    #define EXPBD_IRQ_MASK          (0x1 << 7)
    #define MSINS_MASK              (0x1 << 6)
    #define PENIRQ_MASK             (0x1 << 5)
    #define UCB1400_IRQ_MASK        (0x1 << 4)
    #define ETHERNET_IRQ_MASK       (0x1 << 3)
    #define USBCD_MASK              (0x1 << 2)
    #define USIMCD_MASK             (0x1 << 1)
    #define MMCCD_MASK              (0x1)

	#define INTMSK_RESERVED_BITS	(0xFFFF0000)
    #define INTMSK_SETCLR_RESERVED_BITS	(0xFFFF1100)

    //
    // PCMCIA Socket 0 Status/Control
    //

    // Masks
    //
    #define PCMCIA_S0_nIRQ_MASK         (0x1 << 10)
    #define PCMCIA_S0_nSPKR_BVD2_MASK   (0x1 << 9)
    #define PCMCIA_S0_nSTSCHG_BVD1_MASK (0x1 << 8)
    #define PCMCIA_S0_nVS_MASK          (0x3 << 6)
    #define PCMCIA_S0_nCD_MASK          (0x1 << 5)
    #define PCMCIA_S0_RESET_MASK        (0x1 << 4)
    #define PCMCIA_S0_PWR_MASK          (0xF)

    // Constants
    //
    #define PCMCIA_S0_PWR_A1VCC         (0x1 << 3)
    #define PCMCIA_S0_PWR_A0VCC         (0x1 << 2)
    #define PCMCIA_S0_PWR_A1VPP         (0x1 << 1)
    #define PCMCIA_S0_PWR_A0VPP         (0x1)


    //
    // PCMCIA Socket 1 Status/Control
    //

    // Masks
    //
    #define PCMCIA_S1_nIRQ_MASK         (0x1 << 10)
    #define PCMCIA_S1_nSPKR_BVD2_MASK   (0x1 << 9)
    #define PCMCIA_S1_nSTSCHG_BVD1_MASK (0x1 << 8)
    #define PCMCIA_S1_nVS_MASK          (0x3 << 6)
    #define PCMCIA_S1_nCD_MASK          (0x1 << 5)
    #define PCMCIA_S1_RESET_MASK        (0x1 << 4)
    #define PCMCIA_S1_PWR_MASK          (0xF)

    // Constants
    //
    #define PCMCIA_S1_PWR_A1VCC         (0x1 << 3)
    #define PCMCIA_S1_PWR_A0VCC         (0x1 << 2)
    #define PCMCIA_S1_PWR_A1VPP         (0x1 << 1)
    #define PCMCIA_S1_PWR_A0VPP         (0x1)





#endif
